A typical analog video signal 23 for driving an analog video display is illustrated in FIG. 1. As shown in FIG. 1, the analog video signal 23 is a composite signal having lines of analog data 24 combined with other sweep and synchronization (sync) signals. The composite analog video signal 23 of FIG. 1 generally comprises the following: a horizontal period 11 (a horizontal line), horizontal active time 12, horizontal blank (Hblank) time 13, horizontal front porch 14, horizontal sync (Hsync) period 15, horizontal back porch 16, vertical period 17 (a frame), vertical blank (Vblank) time 18, vertical front porch 19, vertical sync (Vsync) period 20, vertical back porch 21. During the front and back porches, the analog video signal 23 exhibits a blank amplitude level, and during sync periods, the analog video signal 23 exhibits a sync amplitude level.
Typically, the horizontal front porch 14 permits the electron beam associated with a raster display (not shown) to turn off before the beam sweeps from the end of a horizontal scan line to the beginning of the next horizontal scan line. The horizontal sync period causes the electron beam to move to the beginning of the next horizontal scan line and/or to reset counters and other support circuitry. The horizontal back porch 16 permits initialization of the electron beam and other support circuitry prior to acting upon a new scan line. Furthermore, the vertical front porch 19 permits the electron beam associated with the raster display to turn off before the beam sweeps from the end of a frame to the beginning of the next frame. The vertical sync period permits the electron beam to change frames. The vertical back porch 21 permits initialization of the electron beam and other support circuitry prior to acting upon a new frame.
If the analog video display is multicolor, then there would generally be one of the analog video signals 23 allocated to each color, such as for red, green, and blue. However, oftentimes only one of the analog video signals 23, for instance, the one allocated to green, has the sync levels 15, 20.
Recently, there has been a trend in the industry toward developing video displays which are driven by digital video signals as opposed to analog video signals. An example of such a digital video display is the model LQ12D011 TFT LCD flat panel display manufactured and made commercially available by the Sharp Corporation, Japan. Thus, it has recently been desirable to convert the analog video signal 23 of FIG. 1 into a digital video signal for driving a digitally-controlled display. In the process of converting the analog video signal 23 into a digital video signal, the analog data 24 is converted to a series of digital codes, depending upon its amplitude at a given point in time. For Sharp's digital display device, the analog data 24, which typically represents 256 different intensity levels for a particular color, must be converted to only 8 intensity levels (for instance, levels 0 through 7) per color. The lowest possible color intensity level is commonly referred to as the "black" level, whereas the highest possible color intensity level is commonly referred to as the "white" level.
FIG. 2 illustrates a conventional analog-to-digital interface system 21 for converting the analog video signal 23 (FIG. 1) on connection 26 to a digital video signal on connection 43 for driving a digitally-controlled display 25, for example, Sharp's model LQ12D011 TFT LCD flat panel display. The analog video signal 23 is input to the system 21 on connection 26 via a transmission line, commonly a coaxial cable or other like analog communications interface. A dot clock generator 28 produces a dot clock signal 29 based upon the analog video signal 23 on connection 26, sometimes by monitoring the spacing of Hsync periods 15 within the analog video signal 23. An analog-to-digital converter (ADC) 32 converts the analog video signal 23 to a digital video signal at ADC output connection 33 under the control of the dot clock signal on the connection 29a. The digital video signals are stored in a memory 34, such as a FIFO buffer, line buffer, or frame buffer (for instance, a video random access memory (VRAM)). Under the control of the control logic 36, the pixel data is transferred from the memory 34 to buffers/drivers 42 and ultimately to the digitally-controlled display 25.
Sometimes, the display 25 is designed to have the same timing parameters as the analog video signal 23. These timing parameters generally include the frame refresh rate, or rate at which a frame of pixel data is displayed or transferred, front porches 14, 19, back porches 16, 21, and sync periods 15, 20, as indicated in FIG. 1. In these circumstances, there are no timing problems because pixel data is transferred to and from the memory 34 under the control of the control logic 36 at generally the same rate at which the system 21 receives the analog data 24 within the analog video signal 23 on input connection 26. In other words, the blank and sync levels (FIG. 1) are aligned in time with the corresponding periods on connection 43 of FIG. 2. The aforementioned approach is that which most display manufacturers have taken. However, this approach is undesirably inflexible in that it requires the incoming analog video signal and the display 25 to have substantially the same timing parameters as described.
Another approach is to implement a separate display oscillator within the control logic 36 for generating the sync signals for the display 25. In this approach, the display clock signal is inherently asynchronous with the dot clock signal produced by the dot clock generator 28. This approach provides for greater flexibility than other prior art embodiments. If the timing parameters of the analog signal 23 change and/or the requirements of the display 25 change, ideally only an oscillator need be changed to accommodate the new system requirements. However, although this approach exhibits great promise in terms of flexibility, it is problematic in getting the two clock domains to efficiently and reliably interact at high frequencies. Specifically, there are problems associated with continuously and concurrently transferring data to and from the memory 34 at very different high frequencies. Most attempts to accomplish the foregoing have resulted in very apparent visual distortion on the screen of the display 25.